Digital phase comparison checking circuit



Feb. 7, 1967 Filed Jan. .25, 1963 L.. U. C. KELLING DIGITAL PHASE COMPARISON CHECKING CIRCUIT 5 Sheets-Sheet, l

COMMA/VD /D//SE PULSE' W/DTH Feb. 7, 1967 L. U. C. KELLING DIGITAL PHASE COMPARISON CHECKING CIRCUIT Filed Jan. .23, 1963 3 Sheets-Sheet 2 Feb. 7, 1967 L. U. C. KELLING 3,303,421

DIGITAL PHASE COMPARISON CHECKING CIRCUIT Filed Jan. .23, 1963 5 Sheets-Sheet 3 #MMW- 500 CL 06% S/GA/LS *'l @L @ce 0 (QJ 5mm /Wmmm 250 Kc'. l

XFC (b) 334 y/-c (C) 554 X Y (0952202 BMS ZFC (e) 333 BWI/f y United States Patent 3,303,421 DIGITAL PHASE COMPARISON CHECKING CKRCUHT Leroy U. C. Kelling, Waynesboro, Va., assigner to General Electric Company, a corporation of New York Filed Jan. 23, 1963, Ser. No. 253,310 3 Claims. (Cl. 324-83) The invention relates to a checking circuit, and particularly to a circuit for checking the relative phase or time variations of two or more signals such as in a numerical control system.

In a numerical control system lfor either positioning or contoiuring an object, input data from a source such as punched tape is applied to command phase generators which convert this data to signals that vary at a time determined by the data characteristics. The signals from the command phase generators are applied to a comparison circuit along with signals from a position feedback device that vary at a time determined by the feedback device. The comparison circuit compares the command phase generator signals and the position feedback signals to produce an error signal indicative of the time differences (hence phase relation) between the command and feedba-ck signals. This error signal is applied to a servo device that positions or moves the object in accordance with the input data. Since the command phase generator vsignals are compared with the position lfeedback signals on the basis of their relative time variations or phases, it is desirable that the command phase generator signals, as produced by the system, be accurate and precise. If the command phase generator signals have any error, this error will result in an erroneous object motion or position. In a machine tool, such an error can result in work that is the wrong size, shape, or dimension.

Accordingly, an object of the invention is to provide an improved circuit that checks the relative time or phase 1 variations of two or more signals.

A more specific object of the invention is to provide an improved circuit for checking command signals generated in a numerical control system to detect any error in the time variations of such command signals.

Briefly, the checking circuit of the invention compares the phase or time variations of a rst signal with the phase or time variation of an inverted second signal and produces an error signal if the two phase or time variations do not coincide. The checking circuit also compares the phase or time variations of an inverted Iirst signal with the phase or time variations of the second signal and produces an error signal if the two phase or time variations do not coin-eide. The comparisons of a lirst signal with the inverte-d second signal, and the comparison of the second signal with the inverted rst signal provide a double check of the two signals, and enables an error to be detected and indicated if there is any difference in the phase or time variations. It will be appreciated that more than two comparisons may be made on the basis of first and second signals, first and third signals, or on any other basis using one or more of the signals as the common comparison signal.

The invention is particularly pointed out in the claims. The invention, its structure, its operation, and further objects and advantages may 'be better understood by reference to the following description taken in connection with the accompanying drawing, in which:

FIGURE 1 shows a block diagram of a numerical control system in which the checking circuit of the invention may be use-d;

FIGURE 2 shows a schematic diagram of one embodiment of the checking circuit in accordance with the invention; and

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FIGURE 3 shows waveforms for explaining the operation of the checking circuit of the invention.

In the specification, a brief -description will be given of a numerical control system in which the checking circuit of the invention can be used. Next, a -brief explanation of the logic circuits used in the checking circuit will be given. Finally, the checking circuit will be described and its operation will be explained.

Numerical control system While the checking circuit of the invention was designed for and has been used with a numerical control system such as shown in F'IGURE 1, the checking circuit can be used to check the phase or time variations of other signals. The numerical control system of FIGURE l is known in the art, a more detailed description Ibeing given in a copending application of Leroy AU. C. Kelling entitled, Data Conversion System, filed November 21, 1962, Serial No. 239,145. The numerical control system of FIGURE 1 moves work along X and Y axes, and moves with a drill along a Z axis, the three axes usually being perpendicular to each other. rThe control system includes an X axis circuit 11), a Y axis circuit 11, and a Z axis cir-cuit 12 whose mechanical outputs are indicated by dashed lines leading to the work and drill. The X axis circuit 10 is enclosed by dashed lines which include further detailed block diagrams of the X axis circuit. Since the Y axis and Z axis circuits 11, 12 contain similar or equivalent block diagrams, these circuits 11, 12 are not shown in the same detail as the X axis circuit 1i). Additional functions can also be provided. Operation or movement of the work and the drill is controlled by numerical data input equipment 13. This equip-ment 13 provides numerical data representative ofthe desired position or motion of the work relative to the drill, and further representative of the desired motion of the drill. This data is applied to a readin control 14 whose output is applied to the X, Y, and Z axis circuits 11i, 11, 12, to a position feed rate command phase generator 15, and to the checking circuit 16. A timing generator 17 provides timing or clock signals to various circuits in the system including the X, Y, and Z axis circuits 10, 11, 12, the read-in control 14, the position feed rate command phase generator 15, and the checking circuit 16. The generator 17 preferably produces square wave pulses havin-g a frequency of say 250 kilocycles, this being a period of 4 microseconds per cycle. These pulses provide the carrier by which command signals are transported throughout the control system.

In the X axis circuit 10 (and therefore in the Y and Z axis circuits I11, 12 also), pulses from the timing generator 17 and data from the read-in control 14 are applied to coarse, medium, and tine X axis command phase generators 30, 31, 32. These generators produce command signals having coarse, medium, and fine resolution. These command signals vary between two values at a time with respect to the timing generator signals that is determined 1by the numerical data being applied. Thus, the phase of these signals, or the time of their variations, indicates the commanded signal. These coarse, medium, and fine signals are applied to end zone phase comparators 34 which compare the coarse, medium, and tine command signals with respective or corresponding coarse, medium, and fine feedback signals which are produced by X axis feedback devices 35. The feedback signals have a similar time variation or phase which indicates the position of the work in coarse, medium, and ine increments along the X axis. The comparators 34 produce error signals which are applied to an X axis position servo 33. The mechanical output of this servo 33 is indicated by dashed lines, and is applied to the feedback devices 35 and also to the work. The position servo 33 moves the feedback devices 35 and the work in a direction called for by the error signal produced by the comparators 3-4. As the feedback devices 35 and the work are moved, they will eventually reach a point at which the feedback devices 35 produce signals which have the same time variation or phase as the command phase generator signals so that no further error signal is produced. At this time, motion of the work along the X axis stops. If the system is functioning properly, the work will be positioned along the X axis at the desired commanded position.

Positioning or movement along the Y axis and Z axis is accomplished in the same or similar manner. Therefore, no further explanation will be given for these axes.

The system may move the Work at a velocity commanded by the numerical data input equipment 13. This is achieved by the position feed rate command phase generator 15 which produces feed rate signals similar to those produced by the X axis command phase generators 30, 31, 32. The feed rate signals are applied to a pulse width modulator 18. The ouput from the modula- The checking circuit of the invention utilizes digital techniques which include logic circuits of known elements or building blocks. There are many publications describing such elements, one such publication being a book entitled, Design of Transistorized Circuits for Digital Compute-rs, by A. I. Pressman, John F. Ryder Publisher, Inc., New York, 1960. This book discloses a number of actual circuits for accomplishing the various logic functions including gates and dip-Hops. Persons skilled in the art will, after an explanation of the symbols shown, appreciate that many different actual circuits may be utilized to provide the respective functions indicated by the symbols. In the subsequent explanation, tw-o logic terms will be used, these being logic 1 and logic 0. For this explanation, a logic 1 is provided by zero volts, and a logic 0 is provided by plus six volts.

In FIGURE 2, one frequently used log-ic symbol is a multiple (two) input NOT AND gate 40 (i.e., an AND gate with inversion at each of its inputs). In this application, as is known to those skilled in the a-rt, this gate 40 is sometimes called a NOR gate. In logic terms, the gate 40 pr-oduces a logic 0 at its output if any one of its inputs is at a logic l. FIGURE 2 also shows a three input NOR gate 54 and a six input NOR gate 49. These gates 54, 49 also produce a logic at their outputs if any one of their inputs is at a logic 1. A two input OR NOT gate 53 (i.e., an OR gate with inversion at its output) is also shown in FIGURE 2. This gate 53 is also referred to as a NOR gate. In logic terms, the gate 53 produces a logic 0 at its output if any one of its inputs is at a logic 1. FIGURE 2 also shows a six input NOR gate 48. The NOT AND and the OR NOT gates exemplied above are functionally, and may be structurally, the same. The

two types of gates are shown to assist persons in apply-.

ing their logic understanding to the circuit. FIGURE 2 also shows an inverter 41. The purposes of this inverter 41 is simply to reverse the logic of an applied signal. If a logic 1 is applied to the input of the inverter 41, a logic v0 is produced at its output; and if a logic 0 is applied to the input of the inverter 41, a logic 1 is produced at its output.

FIGURE 2 also shows two steered flip-flops, one being the check time active-FF. These Hip-flops have their terminals labeled to assist in this explanation. Outputs from the flip-flops are taken from the terminals 1 and 0. When the ipilop is set, it is in the one state with terminal 1 at a logic 1 and terminal 0 at a logic Il. When the flipflop is reset, it is in the zero state with terminal 1 at a logic 0 and terminal 0 at a logic 1. The flip-flop may be controlled by a number of inputs which include: a set input SI, a reset input RI, a set steering input SS, a reset steer ing input RS, a set trigger input ST, and a reset trigger input RT. A logic 1 applied to the set or reset inputs Sl or RI sets or resets the ilip-ilop respectively for the durad tion of the logic Land subsequently if no further signals are applied to the flip-dop. A logic 0 at the set or reset steering input SS or RS for a predetermined time prior to a trigger pulse steers the flip-flop, and permits the ipflop to be set or reset by a trigger pulse change from a logic 1 to a logic 0 at either the set trigger input ST or the reset trigger input RTrespectively. The flip-flop remains so set or reset after removal of the-se signals and until further signals are applied. In the particular application of the ilip-flops in FIGURE 2, all of the dip-flop terminals are not needed or used. 1

FIGURE 2 shows a number of legends having a combination of letters or a combination of letters and numbers. Some of these legends have a line above them.

Y For example, the legend XFC and the legend XFC appear. The purpose of the line 'above such a legend is to indicate that the signal designated by the legend is inverted in its logic. T-hus, the legend XFC stands for the X fine command. The legend XFC stands for the X ne command inverted. Thus, when the X tine command is at a logic 1, its inversion is at a logic 0. When the X fine command is at a logic 0, its inversion is at a logic 1.

Checking circuit- Description The checking circuit of the invention checks the time variation of signals (hence their phase) by a lcomparison of the time variation of a iirst signal with the time varia tion of the inversion of a second signal, and by a comparison of the time variation of the inversion of the rst signal with the time variation of the second signal. For thenumerical control system shown in FIGURE 1, this is done by a comparison of the X command signals and the Y command signals, by a comparison of the X command signals and the Z command signals, 'and by a comparison of the X command signals with the position feed rate (PFR) signals. These comparisons are made in response to check codes (provided by the numerical data input equipment) having predetermined numbers. If lany one of these comparisons produces an error, at anyV point in the comparison, an error signal is produced. In FIG-4 URE 2, these comparisons are respectively made by three groups of gates set off Iby dashed lines for X versus Y, X ve-rsus Z comparison, and X versus PFR. In FIGURE 2, the legends are coded with X, Y, or Z followed by F, M, or C for tine, medium, or coarse, followed by the letter C for command. In addition, the position feed rate signal from the generator 1S of FIGURE 1 is indicated by the legend PFR. The legend AF means auxiliary function, and the number following this legend indicates the number needed to produce the auxiliary function. Finally, the legend NPCC stands for numerical positioning check command signal.

In the X versus Y comparison section, it will be seen that combinations of the X fine, medium, and coarse command signals and their inversions, and the Y ne, medium, and coarse command signals and their inversions are respectively applied to the gates 42-4'7. Specically, the X ne command signal and the inverted Y line command signal are applied to the gate 42, the inverted X fine command signal and the Y fine command signal are applied to the ygate 43, the X medium command signal and the inverted Y medium command signal are applied to the gate 44, the inverted X medium command signal and the Y medium command signal are applied to the gate 45, the X coarse ycommand signal and the inverted Y coarse command signal are applied to the gate 46, and the inverted X coarse command signal and the Y coarse command signal are applied to the gate 47. The outputs of these gates 42-47 are applied to the six input gate 48. The output of this gate 48 is applied to an X versus Y error bus which is coupled to the six input gate 49. The second input of this gate 49 is derived from the check time active flip-Hop. The check time active ilip-ilop is set by a disc-riminator blanking signal when the checking circuit is to be active or used. The check time .active ip-ilop provides itself with set and reset steering from its one Iand zero terminals respectively. The zero terminal of the check time active Hipop is applied to the gate 40 along with the numerical positioning check command signal. When the check time active flip-dop is set, its zero terminal supplies a logic to the gate 40 along with the logic 0 from the numerical positioning check command to produce a logic l which is inverted by the inverter 41. This logic 1 is inverted to a logic 0 on the code 20 bus and makes the gates 49, S4, S permissive as far as the code 20 `bus is concerned. The output of the gate 40 is inverted by the inverter 41 and applied to the code 20 bus. This code 20 bus is at a logic 0 if the proper check code (a ten value of 2) has been applied to the system. As will be explained further, the check codes contemplated were the numbers 20, 21, or 22 for the various comparisons. The other four inputs to the gate 49 are derived from the auxiliary function generator flip-flops having unit values of l, 2, 4, and 8.v For a check code of 20, all these flip-flops should be reset so that the signals on their output terminals are all logic 0.

In the X versus Z comparison, the check code 21 requires that the auxiliary function iip-llop 1 having a unit value of 1 should be set. The inversion of this signal on the output terminal of this hip-flop is a logic v0. In the X versus PFR comparison, the check code 22 requires that the auxiliary ip-op having a unit value of 2 be set so that the inversion of the signal on the output terminal is a logic 0.

Outputs from the gates 49, 54, 55 are applied to the gate 50, the output of which is applied to the set steering terminal of the check error flip-flop. If any error is present, from any of the comparison circuits, a logic l is applied to the gate 50 to produce a logic 0 at the set steering terminal of the check error flip-flop. This provides set steering for the flip-op and on the next clock Signal, this flip-flop becomes set. Normally this ip-flop is reset through the closed contacts MTR. These contacts are the machine operators test relay which are .opened when the checking circuit is to be used. When C hec-king circuit-Operation The operation of the checking circuit will be explained in connection with several examples illustrated by the waveforms shown in FIGURE 3. In FIGURE 3, all the waveforms are plotted against a common time axis. FIGURE 3a shows the clock signals produced by the timing generator 17 of FIGURE l, these clock signals being square wave signals which vary at a 250 kilocycle rate between a logic l and ia logic O. FIGURE 3b shows a signal derived from the X axis fine command phase generator. FIGURE 3c shows a signal derived from t-he Y axis ne command phase generator. FIGURE 3d shows the output of the X versus Y comparison error bus.

FIGURE 3e shows a signal derived from the Z axis line command phase generator. And FIGURE 3f shows the output of the X versus Z comparison error bus.

Before a check is made, the check time active flip-op has been reset by a trigger signal derived from t-he clock signals. Its zero terminal is at a logic 1, and its one terminal is at a logic 0 so that this ip-flo-p has set steering. When a check is to be made, a code of 20, 21, or 22 is supplied. In response to the ten value of 2, a discriminator blanking signal is applied to the set Vtrigger terminal of the check time active ilip-op to set this ilipflop. At the same time, an inverted numerical positioning check command signal of logic 0 is applied to the gate 4i). With the check time active ip-flop set, both inputs of the gate 40 are lat a logic 0 and it produces a logic l. This logic 1 is inverted by the inverter 41 to a logic 0 so that the code bus 20 is at a logic 0 to the gates 49, S4, 5S. For an X versus Y comparison, check code 20 is supplied. This check code 20 resets the auxiliary function flip-flops having unit values of l, 2, 4, and 8. Therefore the lower four inputs of the gate 49 are supplied with a logic 0. Then, a series of line, medium, and coarse command signals are applied to the X and Y command phase counters. The number of command signals so applied depends u-pon the checks of the phase generators which must be made. For example, the number 334 may have particular significance in terms of introducing or finding trouble or a fault in the system. If the X and Y command phase generators are functioning properly, their outputs will have the same phase or will vary at the same points in time. This is exemplified by the X fine command signal of FIGURE 3b and the Y fine command signal of FIGURE 3c. It is to be understood that the medium and coarse commands are also producing signals and are also being Compared at the same time. At the time t1, the X tine command signal goes from a logic l to a logic 0 and the Y line command goes from a logic 1 to a logic 0 also. The inverted X and Y ne commands go from a logic 0 to a logic 1 at this time t1 also. Thus',A the gate 42 has a logic 0 applied to its input by the X line command anda logic 1 applied to it by the inverted Y fine command. The gate 43 has a logic 1 applied to its input by the inverte-d X iine command and a logic O applied to itsy input by the Y ne comm-and.l One of the inputs (i.e., YFU) to the gate 42 is at a logic 1, Iand one of the inputs (i.e., XFC) to the gate 43 (i.e., the input XFG) is at a logic 1 also. Therefore the gates 42, 43 both produce a logic 0 at their outputs. If the medium and coarse commands are in proper phase or time relationship, the gates 44, 45, 46, 47 likewise produce a logic 0 at their outputs. With all the inputs of the gate 48 at a logic 0, indicating proper phase relationships of the signals, the gate 48 produces a logic 1 on the X versus Y error bus as shown in FIGURE 3d. This logic 1 causes the gate 49 to produce a logic 0 at its output. If the other comparison circuits, namely the X versus Z and X versus PFR, have signals applied to them which are in the proper phase or time relationships, the gates S4, 55 likewise produce a logic 0 at their respective outputs. Thus, the gate 50 has all its inputs at 'a logic 0 and produces a logic 1 at its output. This logic l is applied to the set steering terminal of the check error ip-flop and is the incorrect logic value and prevents this flip-flop from becoming set by a clock signal. When both the command signals return to logic 1 at time t3, no error signal is produced.

If, however, one of the inputs to the gate 50 is at a logic 1, indicating an error in one of the comparison circuits, then the gate 50 produces a logic 0 at its output which provides set steering for `the check error ilip-op. The next clock signal at the set trigger input of the check error ip-flop sets this flip-Hop and a logic 0 is applied to the gate 56. The gate 56, if the relay contacts are open, produces a logic 1 error signal which indicates t0 the openator that an error in the signal has occurred or taken place. FIGURE 3 shows the conditions in a comparison which would produce an error signal. If, in the X versus Z comparison, the Z axis fine command phase generator produced `a signal of 333 instead of 334, as shown in FIGURE 3e, this signal would vary from a logic l to a logic 0 at the time t2 instead of the time t1 as it should. Thus, for the X versus Z comparison, the X fine command signal is at a logic between the times t1 and t2, while the Z fine command signal is at a logic l between the times t1 and t2. During this interval, both inputs (XFC and ZIT-) to the gate 57 are at a logic 0, while both inputs (XFC and ZFC) to the gate 58 are at a logic 1. The gate 57 produces a logic 1 at its output which, when applied to the gate 50, causes a logic O to be produced on the X versus Z error bus. With the check code 21 being applied, the auxiliary function flipiiop having a unit value of 1 is set and its inverted output is at a logic 0. Therefore, all inputs to the gate 54 are at a logic O and the gate S4 produces a logic 1 which is applied to the gate 50. This causes the gate S0 to produce a logic 0 set steering for the check error iiip-fiop. On the next clock pulse, an error will be indicated. At the interval between times t3 and t4, another error will be indicated. This is shown in FIGURE 3 f.

In addition to checking commanded position, the checking circuit of the invention can also check commands of pulse feed rate,.or any other command which :has a variation at a particular time. In addition, any number of commands may be compared simultaneously as indicated by the X versus Y comparison of fine, medium, and coarse command signals as opposed to the X versus PFR comparison of only an X command and pulse feed rate command signal. Any two or more signals may be compared at the same time in accordance with the invention, and any number of such comparisons may be combined by appropriate logic gates of the requisite number of inputs. And, any sort of code to make la comparison operable can be used. Thus, thecheck code 20 may be applied so that only an X versus Y comparison takes place, or a check code 20 and 21 may be simultaneously used to provide a simultaneous X versus Y and X versus Z comparison, or a check code 20, a check code 21, anda check code 22 may be provided for three simultaneous comparisons. In one practical embodiment, it was found that simultaneous comparisons of all signals could be used first, and if yan error were indicated, then individual comparisons could be made to localize the error. It will thus be seen that the check circuit provides a new and improved system for checking signals whose phase or whose time variations must occur at .a predetermined time. While the invention has been described with reference to la particular embodiment, it is to be understood that modifications may be made by persons skilled in the art without departing from the spirit of the invention or from the scope of the claims.

What I claim as newy and desire to secure by Letters Patent ofthe United States is:

1. In a system wherein a command is represented by a plurality of binary coded command signals that vary in their binary characteristic at a time determined by said command, a circuit for checking said time of variations of said command signals comprising a `iirst gating means for -comparing the time of binary variation of a first corn- Inand signal with the time of binary variation of the inversion of a second command signal, said first gating means producing a binary signal output only when there is a time diiierence in variation of said two signals, a second gating means for comparing the time of binary variation of the inversion of said first command signal with the time of binary variation of said second commandsignal, said second gating means producing a binary output only when there is a time difference in variation of said two signals, and means coupled to the outputs of said rst 8 and second gating means for producing a binary output signal whenever a binary output signal is produced at the output of either of said first and second gating means.

2. In a system wherein a command is represented by a plurality of binary coded command signals that vary in their binary characteristic at a time determined by said command, a circuit for checking said time of variations of said command signals comprising a iirst circuit for comparing the time of binary variation of a first command signal with the time of binary variation of the inversion of a second command signal and producing an error signal in response to a time difference in variation of said two signals, a second circuit for comparing the time of binary variation of the inversion of said first command signal with the time of binary variation of said second command signal and producing an error signal in response to a time difference in variation of said two signals, a third circuit for comparing the time of binary variation of said iirst command signal with the time of binary variation of the inversionfof a third command signal and producing an error signal in response to a time difference in variation of said two signals, a fourth circuit for comparing the time of binary variation of said inversion of said first command signal with the time of binary variation of said third command signal and producing an error signal in response to a time difference in variation of said two signals, and means coupled to said four circuits and activated by a checking signal for producing an output signal in response to an error signal from any one of said four circuits.

3. In a system wherein a command is represented by first and second binary coded X command signals that vary in their binary characteristic at a time determined by said X command, and Vwherein a command is further represented by first and second binary coded Y command signals that vary in their binary characterist-ic at a time determined by said Y command, a circuit for checking said time of variations of said command signals comprising a first circuit for comparing the time of binary variation of said first X command signal with the time of binary variation of the inversion of said first Y command signal and producing an error signal in response to a time difference in variation of said two signals, a secondcircuit for comparing the time of binary variation ofthe inversion of said iirst X command sginal with the time of binary variation of said first Y command signal and producing an error signal in response to a time difference in variation of said two signals, a third circuit for comparingthe time of binary variation of said second X command signal with the time of binary variation of the inversion of said second Y command signal and producing an error signal in response to a time difference in Variation of said two signals, a fourth circuit for comparing the time of binary variation of the inversion of said second X command signal with the time of binary variation of said second Y command signal and producing an error signal in response to a time difference in variation of said two signals, and means coupled to said four circuits and activated by a checking signal for producing an output signal in response to an error signal from any one of said four circuits.

References Cited by the Examiner UNITED STATES PATENTS 2,933,682 4/1960 MOultOn et al 324-82 X 2,985,773 5/1961 Dobbie 324-79 X 2,988,696 6/1961 Pihl 32.4--83 y3,016,517 6/1962 Saltzberg 324--83 X 3,209,254 9/1965 Hossmann g 324--83 WALTER L. CARLSON, Primary Exafm'ner.l

RUDOLPH V. ROLINEC, Examiner. A, E. RICHMOND, Assistant Examiner.y 

1. IN A SYSTEM WHEREIN A COMMAND IS REPRESENTED BY A PLURALITY OF BINARY CODED COMMAND SIGNALS THAT VARY IN THEIR BINARY CHARACTERISTIC AT A TIME DETERMINED BY SAID COMMAND, A CIRCUIT FOR CHECKING SAID TIME OF VARIATIONS OF SAID COMMAND SIGNALS COMPRISING A FIRST GATING MEANS FOR COMPARING THE TIME OF BINARY VARIATION OF A FIRST COMMAND SIGNAL WITH THE TIME OF BINARY VARIATION OF THE INVERSION OF A SECOND COMMAND SIGNAL, SAID FIRST GATING MEANS PRODUCING A BINARY SIGNAL OUTPUT ONLY WHEN THERE IS A TIME DIFFERENCE IN VARIATION OF SAID TWO SIGNALS, A SECOND GATING MEANS FOR COMPARING THE TIME OF BINARY VARIATION OF THE INVERSION OF SAID FIRST COMMAND SIGNAL WITH THE TIME OF BINARY VARIATION OF SAID SECOND COMMAND SIGNAL, SAID SECOND GATING MEANS PRODUCING A BINARY OUTPUT ONLY WHEN THERE IS A TIME DIFFERENCE IN VARIATION OF SAID TWO SIGNALS, AND MEANS COUPLED TO THE OUTPUTS OF SAID FIRST AND SECOND GATING MEANS FOR PRODUCING A BINARY OUTPUT SIGNAL WHENEVER A BINARY OUTPUT SIGNAL IS PRODUCED AT THE OUTPUT OF EITHER OF SAID FIRST AND SECOND GATING MEANS. 